Single layer low cost wafer level packaging for sff sip

ABSTRACT

In one embodiment of the invention, a system in package (SiP) is described which includes a plurality of device components with different form factors embedded within a molding compound layer. A surface for each of the device components is coplanar with a surface of the molding compound layer, and a single redistribution layer (RDL) formed on the coplanar surfaces of the molding compound layer and the plurality of device components. An active device die is electrically bonded to the single RDL directly vertically adjacent the plurality of device components. In an embodiment, the SiP is electrically connected to a circuit board with the active device die between the single RDL and the circuit board. In an embodiment, the SiP is electrically connected to a circuit board with the active device die over the single RDL and the circuit board.

This is a Divisional of application Ser. No.: 13/532,119 filed Jun. 25,2012, which is hereby incorporated by reference.

BACKGROUND

Continued reduction in end product size of mobile electronic devicessuch as smart phones and ultrabooks is a driving force for thedevelopment of packaging with a small form factor (SFF). System inpackage (SiP) technologies have been developed to incorporate multiplecomponents into a single package to reduce the system board space andboard mounted height.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional side view illustration of a plurality ofdevice components placed on a carrier substrate in accordance with anembodiment of the invention.

FIG. 2 is a cross-sectional side view illustration of a molding compoundlayer formed over the plurality of device components of FIG. 1 inaccordance with an embodiment of the invention.

FIG. 3 is a cross-sectional side view illustration of the carriersubstrate of FIG. 2 removed in accordance with an embodiment of theinvention.

FIG. 4 is a cross-sectional side view illustration of a singleredistribution layer and buildup layer formed over the structure of FIG.3 in accordance with an embodiment of the invention.

FIG. 5 is a cross-sectional side view illustration of an active devicedie electrically bonded to the single redistribution layer of FIG. 4 inaccordance with an embodiment of the invention.

FIGS. 6A-6C are cross-sectional side view illustrations of varioussequences for the formation of conductive bumps in accordance withembodiments of the invention.

FIG. 7 is a cross-sectional side view illustration of singulatedpackages in accordance with an embodiment of the invention.

FIG. 8 is a cross-sectional side view illustration of a packageelectrically connected to a circuit board in accordance with anembodiment of the invention.

FIG. 9 is a cross-sectional side view illustration of a packageelectrically connected to a circuit board with cored solder balls inaccordance with an embodiment of the invention.

FIG. 10 is a cross-sectional side view illustration of a packageelectrically connected to a circuit board with interposers between bumpsin accordance with an embodiment of the invention.

FIG. 11 is a cross-sectional side view illustration of an underfillmaterial between a buildup layer and an active device die in accordancewith an embodiment of the invention.

FIG. 12 is a cross-sectional side view illustration of an active devicedie electrically connected to a single redistribution layer with wirebonds in accordance with an embodiment of the invention.

FIG. 13 is a cross-sectional side view illustration of a devicecomponent electrically connected to both the active device die and thecircuit board in accordance with an embodiment of the invention.

FIG. 14 is a cross-sectional side view illustration of a packageelectrically connected to a circuit board in accordance with anembodiment of the invention.

FIG. 15 is a block diagram illustration of a computing device inaccordance with an embodiment of the invention.

DETAILED DESCRIPTION

Embodiments of the present invention relate to a SiP structure andmethod of forming a SiP structure with SFE In various embodiments,description is made with reference to figures. However, certainembodiments may be practiced without one or more of these specificdetails, or in combination with other known methods and configurations.In the following description, numerous specific details are set forth,such as specific configurations, dimensions and processes, etc., inorder to provide a thorough understanding of the present invention. Inother instances, well-known semiconductor processes and manufacturingtechniques have not been described in particular detail in order to notunnecessarily obscure the present invention. Reference throughout thisspecification to “one embodiment,” “an embodiment” or the like meansthat a particular feature, structure, configuration, or characteristicdescribed in connection with the embodiment is included in at least oneembodiment of the invention. Thus, the appearances of the phrase “in oneembodiment,” “an embodiment” or the like in various places throughoutthis specification are not necessarily referring to the same embodimentof the invention. Furthermore, the particular features, structures,configurations, or characteristics may be combined in any suitablemanner in one or more embodiment.

The terms “over”, “to”, “between” and “on” as used herein may refer to arelative position of one layer with respect to other layers. One layer“over” or “on” another layer or bonded “to” another layer may bedirectly in contact with the other layer or may have one or moreintervening layers. One layer “between” layers may be directly incontact with the layers or may have one or more intervening layers.

In one aspect, embodiments of the invention enable the fabrication ofSiP with a reduced form factor in the x, y, and z directions by placingan active device die directly vertically adjacent, or in the shadow of,an arrangement of passive device components that have different formfactors (x, y, and z). In a particular embodiment directed toward amobile radio frequency (RF) device, RF passive device components and/oractive device components having different form factors (x, y, and z) arefirst assembled on a substrate surface through a wafer level packagingprocess and molded using molding compound. The substrate is removed anda single redistribution layer (RDL) is formed on coplanar surfaces ofthe molding compound layer and the plurality of device components. Asystem on chip (SOC) die such as a radio transceiver integrated circuit(IC) is then assembled bonded to the single RDL directly verticallyadjacent the plurality of device components. In this manner, the passiveand/or active device components and the silicon radio transceiver IC areintegrated in a SiP at wafer level with a single RDL. This approach canprovide for reduced form factor in the x, y, and z directions, and lowercost since a single RDL is used. Furthermore, the fabrication approachmay improve system performance due to shorter interconnects between theradio transceiver IC and the RF device components.

Referring now to FIG. 1, a plurality of device components 102 includingelectrical contacts 104 are placed on a carrier substrate 110. Carriersubstrate can be any planar substrate, such as tape, silicon wafer,glass, metal, or polymer. The plurality of device components 102 mayhave different form factors in any or all of the (x, y, z) dimensions.In the particular cross-sectional side view illustration of FIG. 1, theplurality of device components 102 are illustrated with different x andz dimensions. As illustrated, the device components 102 includeelectrical contacts 104 embedded within or protruding from a bulk areaof the device components 102.

The plurality of device components 102 can be passive device componentsand/or active device components. In one embodiment, all of the devicecomponents 102 are passive device components. In an embodiment, thedevice components 102 include both passive and active device components.For example, passive device components can include any of a band passfilter, capacitor, inductor, resistor, and crystal for clock generation.For example, active device components can include any of a poweramplifier and an RF switch.

Referring now to FIG. 2, a molding compound layer 112 is formed over theplurality of device components 102 and the carrier substrate 110.Molding compound may be any molding compound utilized in packagingtechnologies, and may be applied in a variety of manner including spincoating, injection molding, compression molding, and transfer molding.For example, the molding compound can be a thermosetting material suchas, but not limited to, epoxy resin, phenolic resin, polyimide, andpoly-benzoxasole (PBO). The molding compound may also be filled. In anembodiment, the molding compound comprises approximately 90% filler,such as silica particles. The molding compound layer 112 is then fullycured to solidify the alignment of the device components 102 and providerigidity for handling.

The carrier substrate 110 is then released as illustrated in FIG. 3utilizing a suitable technique such as peeling, laser lift off, andultraviolet (UV) irradiation. As illustrated, the exposed surface 116for each of the device components 102 which was previously in contactwith the carrier substrate 110 is coplanar with the exposed surface 114of the molding compound layer 112 which was previously in contact withthe carrier substrate 110.

Referring now to FIG. 4, a single redistribution layer (RDL) 120 fan-outand buildup layer 122 are formed on the coplanar surfaces 114, 116. Thepatterned RDL 120 with multiple traces 120A-F is first formed, followedby depositing buildup layer 122 over the RDL 120 and patterning thebuildup layer to form a plurality of openings 124, which may exposecontact pads of traces 120A-F. In an embodiment, the single RDL is 7-10μm thick, and the buildup layer 122 is approximately 20-30 μm thick. Inthis manner, the single and thin RDL and buildup layer can reduce the(z) form factor dimension. A variety of dielectric materials may be usedto form buildup layer 122. In an embodiment, a photosensitive polyimideis used. In such an embodiment, the photosensitive polyimide is cured byUV irradiation after patterning to form openings 124.

An active device die 130 is then electrically bonded to the single RDL120 directly vertically adjacent the plurality of device components 102,as illustrated in FIG. 5. In the particular embodiment illustrated, theactive device die 130 is electrically bonded to the single RDL 120 withsolder balls 140. For example, such a connection can be made by pick andplace of the active device die 130 followed by solder reflow, or thermalcompression bonding (TCB). As illustrated, the bump pattern for solderballs 140 of the active device die 130 are aligned with the devicecomponents 102 for minimum lateral routing and fan-out, which can reducethe (x, y) form factor dimensions. In another embodiment illustrated inFIG. 12 and described in more detail in the following description, theactive device die 130 is electrically bonded to the single RDL 120 withwire bonds 154.

Referring now to FIGS. 6A-6C, electrical interconnects 142, such asconductive bumps, may be formed for electrically bonding the single RDLto a circuit board, in accordance with some embodiments. In theembodiments illustrated in FIGS. 6A-6C, the conductive bumps 142 arearranged along a periphery of the single RDL 120. Referring to FIG. 6A,conductive bumps 142 having a height larger than the height higher thansolder balls 140 is placed on the single RDL prior to electricallybonding the active device die 130 to the single RDL 120. Referring toFIG. 6B, conductive bumps 142 having a height larger than reflowedsolder balls 140 and the active device die 130 together are placed onthe single RDL 120 after electrically bonding the active device die 130to the single RDL 120. Referring to FIG. 10, where an interposer isused, conductive bumps 142 are not required to be higher than thereflowed solder balls 140 and the active device die 130.

Conductive bumps 142 can be formed using a variety of processesincluding screen printing or microball ball grid array (BGA). Referringnow to FIG. 6C, conductive bumps 142 can be placed on the board siderather than (or in addition to) on the single RDL, in which case bondingpads 126 in the single RDL 120 are open. For example, where aninterposer is used, conductive bumps 142 can be placed on both the boardside and the single RDL.

Referring now to FIG. 7 the molding compound layer with a plurality ofembedded device components and buildup layer are singluated to form aplurality of system in packages

(SiPs) 100. Thus, while the formation of a single SiP has been describedhereto, multiple SiPs can be manufactured beginning with the samemolding compound layer, etc. In an embodiment, each SiP 100 includes aplurality of device components 102 with different form factors embeddingwithin the singulated molding compound layer 112, where a surface foreach of the device components is coplanar with a surface of the moldingcompound layer 122. A single RDL is formed on the coplanar surfaces ofthe molding compound layer 112 and the plurality of device components102. An active device die 130 electrically bonded to the single RDL 120directly vertically adjacent the plurality of device components 102.Each individual SiP 100 may then be connected to a circuit board. Forexample, the circuit board can be a daughter card which is to be placedon a motherboard of a mobile computing device such as a smart phone orultrabook. Alternatively, the circuit board may be the motherboard.

In an embodiment illustrated in FIG. 8, the SiP 100 is electricallyconnected to circuit board 200 with conductive bumps 142. In anembodiment, bumps 142 are solder bumps. As described above, conductivebumps 142 may have a height larger than reflowed solder balls 140 andthe active device die 130 together.

In the following description of FIGS. 9-14, several variations of theSiP 100 and manner for electrically connecting the SiP 100 to a circuitboard 200 are described. It is to be understood that while the followingvariations are separately illustrated and described, the variations arenot necessarily incompatible with one another, and that many of thevariations may be combined in any suitable manner in one or moreembodiment.

Referring now to an embodiment illustrated in FIG. 9, bumps 142 mayinclude an inner core 144 within an outer shell. Inner core 144 may beformed of a material (e.g copper) which has a higher melting temperaturethan the outer shell (e.g. solder material) of bumps 142 so as toprovide structural height to the system, which may maintain a gapbetween circuit board 200 and active device die 130. Structural heightmay also be maintained through bonding of the SiP 100 to circuit board200 by use of interposers 146 between bumps 142, as illustrated in FIG.10. In the embodiment illustrated in FIG. 10, conductive bumps 142 arenot required to be higher than the reflowed solder balls 140 and theactive device die 130. For example, the conductive bumps 142 can beapproximately the same height as the solder balls 140 prior to reflow.Bumps 142 may have different sizes/heights on the SiP 100 side andcircuit board 200 side of interposers 146.

Referring to FIG. 11, in an embodiment, and underfill material 150 maybe formed between the buildup layer 122 and active device die 130. In anembodiment, the underfill material is applied prior to singulating theSiP.

Referring now to FIG. 12, in an embodiment, the active device die 130 iselectrically connected to the single RDL 120 with wire bonds 154. Thewire bonds 154 may further be protected with encapsulant 152. Wirebonding and encapsulating the wire bonds can be performed prior toelectrically connecting the SiP 100 to the circuit board 200, and can beprior to singulating the SiP 100. In the particular embodimentillustrated, interposers 146 are provided between bumps 142 electricallyconnecting the SiP 100 to the circuit board 200 to create a structuralheight to accept the wire bonds. In another embodiment, cored bumps canbe used to provide the structural height.

Referring now to FIG. 13, in an embodiment, one of the device components102 is electrically connected to a first trace 120G in the single RDLthat is also electrically connected to the active device die 130. Thesame device component 102 is also electrically connected to a secondtrace 120H in the single RDL that is also electrically connected to thecircuit board 200. The specific device component 102 pointed to in FIG.13 may be a passive device component or an active device component.

In one embodiment, the device component 102 is a passive devicecomponent such as a capacitor and is electrically connected to a line202 in the circuit board such as a ground line, power line, or signalline. In such an embodiment, a direct current (DC) coming from a signalport in the active device die 130 may be blocked or rerouted by thepassive device 102 so that the DC current does not travel along thesignal line 202 in the circuit board 200 connected to an antenna (whichis designed to receive only a radio frequency (RF) signal). In anotherembodiment, the passive device component 102 may function as a frequencyselector for a signal line 202 in the circuit board 200 going to anantenna due to the impedance of the signal coming from a signal port inthe active device die 130.

In one embodiment, the device component 102 is an active devicecomponent such as a power amplifier or RF switch, either of which can bebased on a gallium arsenide die. In such an embodiment, the activedevice component 102 may amplify or select a RF signal coming from asignal port in the active device die 130 and transmit the amplified orselected RF signal along a signal line 202 in the circuit board 200which is connected to an antenna. In an alternative embodiment, theactive device die 130 is a SOC die which includes a power amplifier. Insuch an embodiment, the SOC die may transmit an amplified signal throughtrace 120A to a signal line 202 in the circuit board 200 which isconnected to an antenna.

Referring now to FIG. 14, in an embodiment, a SiP 100 is electricallyconnected to a circuit board 200 with the active device 130 over thesingle RDL 120 and the circuit board 200. Such an embodiment may beuseful if the active device die 130 has more connections than just tothe device components 102. In such a case, the (x, y) form factordimension can be reduced with a slightly larger z dimension form factorthan in other embodiments. As previously described, the SiP 100 includesa plurality of device components 102 with different form factorsembedded within a molding compound layer 112, where a surface for eachof the device components 102 is coplanar with a surface of the moldingcompound layer 112. A single RDL 120 is formed on the coplanar surfacesof the molding compound layer and the plurality of device components. Anactive device die 130 is electrically bonded to the single RDL 120directly vertically adjacent the plurality of device components 102. Aplurality of conductive interconnects 164 are arranged along a peripheryof the single RDL 120 electrically connecting the SiP 100 to the circuitboard 120. In the particular embodiment illustrated, the conductiveinterconnects 164 are vias extending through the molding compound layer112 from the single RDL 120 to a backside single RDL 160 and builduplayer 162. Conductive bumps 142 may additionally be used to electricallyconnect the vias 164 to the circuit board 200.

FIG. 15 illustrates a computing device 1000 in accordance with oneimplementation of the invention. The computing device 1000 houses aboard 1002, which may be a circuit board such as a motherboard. Theboard 1002 may include a number of components, including but not limitedto a processor 1004 and at least one communication package 1006 that maybe any of the SiP packages formed in accordance with implementations ofthe invention. The processor 1004 is physically and electrically coupledto the board 1002. In some implementations at least one communicationpackage 1006 is also physically and electrically coupled to the board1002. In further implementations, the communication package 1006 isphysically and electrically coupled to another circuit board such as acard 1008 (e.g. a daughter card), which is physically and electricallycoupled to the board 1002. In further implementations, the communicationpackage 1006 is part of the processor 1004.

Depending on its applications, computing device 1000 may include othercomponents that may or may not be physically and electrically coupled tothe board 1002. These other components include, but are not limited to,volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flashmemory, a graphics processor, a digital signal processor, a cryptoprocessor, a chipset, an antenna, a display, a touchscreen display, atouchscreen controller, a battery, an audio codec, a video codec, apower amplifier, a global positioning system (GPS) device, a compass, anaccelerometer, a gyroscope, a speaker, a camera, and a mass storagedevice (such as hard disk drive, compact disk (CD), digital versatiledisk (DVD), and so forth).

The communication package 1006 may be any of the SiP packages that areformed in accordance with implementations of the invention. Thecommunication package 1006 enables wireless communications for thetransfer of data to and from the computing device 1000. The term“wireless” and its derivatives may be used to describe circuits,devices, systems, methods, techniques, communications channels, etc.,that may communicate data through the use of modulated electromagneticradiation through a non-solid medium. The term does not imply that theassociated devices do not contain any wires, although in someembodiments they might not. The communication package 1006 may implementany of a number of wireless standards or protocols, including but notlimited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE,GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well asany other wireless protocols that are designated as 3G, 4G, 5G, andbeyond. The computing device 1000 may include a plurality ofcommunication packages 1006. For instance, a first communication package1006 may be dedicated to shorter range wireless communications such asWi-Fi and Bluetooth and a second communication package 1006 may bededicated to longer range wireless communications such as GPS, EDGE,GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

The processor 1004 of the computing device 1000 includes an integratedcircuit die packaged within the processor 1004. In some implementationsof the invention, the integrated circuit die of the processor includesone or more devices, such as transistors or metal interconnects. Theterm “processor” may refer to any device or portion of a device thatprocesses electronic data from registers and/or memory to transform thatelectronic data into other electronic data that may be stored inregisters and/or memory.

In various implementations, the computing device 1000 may be a laptop, anetbook, a notebook, an ultrabook, a smartphone, a tablet, a personaldigital assistant (PDA), an ultra mobile PC, a mobile phone, a desktopcomputer, a server, a printer, a scanner, a monitor, a set-top box, anentertainment control unit, a digital camera, a portable music player,or a digital video recorder. In further implementations, the computingdevice 1000 may be any other electronic device that processes data.

In an embodiment, a system in package comprises a plurality of devicecomponents with different form factors embedded within a moldingcompound layer, wherein a surface for each of the device components iscoplanar with a surface of the molding compound layer; a singleredistribution layer is formed on the coplanar surfaces of the moldingcompound layer and the plurality of device components; and an activedevice die is electrically bonded to the single redistribution layerdirectly vertically adjacent the plurality of device components. Theplurality of device components may have a plurality of differentheights, widths, and lengths. The active device die may be electricallybonded to the single redistribution layer with bonds selected from thegroup consisting of solder bumps and wire bonds. A plurality ofconductive interconnects may further be arranged along a periphery ofthe single redistribution layer. A plurality of conductive interconnectsmay be arranged along a periphery of the single redistribution layer. Inan embodiment, one of the device components is electrically connected toa first trace in the single redistribution layer that is electricallyconnected to the active device die, and electrically connected to asecond trace in the single redistribution layer that is electricallyconnected to one of the conductive interconnects.

In an embodiment, the plurality of device components are passive devicecomponents. For example the active device die may include a radiotransceiver integrated circuit, and the passive device componentsinclude a component selected from the group consisting of a band passfilter, capacitor, inductor, resistor, and crystal for clock generation.In an embodiment, the plurality of device components include passivedevice components and an active device component. For example, theactive device die may include a radio transceiver integrated circuit,the active device component may include a component selected from thegroup consisting of a power amplifier and RF switch, and the passivedevice components include a component selected from the group consistingof a band pass filter, capacitor, inductor, resistor, and crystal forclock generation.

In an embodiment a system comprises a circuit board and a system inpackage. The system in package comprises a plurality of devicecomponents with different form factors embedded within a moldingcompound layer, wherein a surface for each of the device components iscoplanar with a surface of the molding compound layer; a singleredistribution layer formed on the coplanar surfaces of the moldingcompound layer and the plurality of device components; and an activedevice die electrically bonded to the single redistribution layerdirectly vertically adjacent the plurality of device components. Aplurality of conductive interconnects are arranged along a periphery ofthe single redistribution layer electrically connecting the system inpackage to the circuit board. The active device die may not be in directcontact with the circuit board. The conductive interconnects can beconductive bumps including an inner core material and outer shellmaterial, with the inner core material having a higher meltingtemperature than the outer shell material. The conductive interconnectscan comprise conductive bumps electrically connected to interposers. Inan embodiment one of the device components is electrically connected toa first trace in the single redistribution layer that is electricallyconnected to the active device die, and electrically connected to asecond trace in the single redistribution layer that is electricallyconnected to the circuit board. For example, the device component can bea passive device component selected from the group consisting of acapacitor and inductor and is electrically connected to a line in thecircuit board selected from the group consisting of a ground line, powerline, and signal line.

The system in package can be electrically connected to the circuit boardwith the active device die between the single redistribution layer andthe circuit board, or with the active device die over the singleredistribution layer and the circuit board. In an embodiment, conductiveinterconnects comprise vias through the molding compound layerelectrically connecting the single redistribution layer to the circuitboard. In an embodiment, the circuit board is a daughter card or amotherboard. In an embodiment, the circuit board is secured within acomputing device such as a tablet or smart phone comprising an antenna,a battery, and a microprocessor electrically connected with the circuitboard.

In an embodiment, a method of assembling a system in package comprisesplacing a plurality of device components having different form factorson a carrier substrate; forming a molding compound layer over the devicecomponents, wherein a bottom surface of the device components iscoplanar with a bottom surface of the molding compound layer and theplurality of device components are embedded within the molding compoundlayer; curing the molding compound layer; removing the carriersubstrate; forming a single redistribution layer on the coplanar bottomsurfaces of the molding compound layer and the plurality of devicecomponents; forming a buildup layer on the single redistribution layer;forming a plurality of openings in the buildup layer; electricallybonding an active device die to the single redistribution layer of thepackage and directly vertically adjacent the plurality of devicecomponents; and singulating the system in package. In an embodiment, themethod further includes placing a plurality of conductive bumps along aperiphery of the single redistribution layer prior to singulating thesystem in package. In an embodiment, the method further includesproviding an underfill material between the active device die and thebuildup layer. In an embodiment, the method further includeselectrically connecting the system in package to a circuit board withthe active device die between the single redistribution layer and thecircuit board. In an embodiment, the method further includeselectrically connecting the system in package to a circuit board withthe active device die over both the single redistribution layer and thecircuit board.

Although the invention has been described with reference to specificembodiments, it will be understood by those skilled in the art thatvarious changes may be made without departing from the spirit or scopeof the invention. Accordingly, the disclosure of embodiments of theinvention is intended to be illustrative of the scope of the inventionand is not intended to be limiting. It is intended that the scope of theinvention shall be limited only to the extent required by the appendedclaims. For example, to one of ordinary skill in the art, it will bereadily apparent that the SiPs and the related structures and methodsdiscussed herein may be implemented in a variety of embodiments, andthat the foregoing discussion of certain of these embodiments does notnecessarily represent a complete description of all possibleembodiments.

Additionally, benefits, other advantages, and solutions to problems havebeen described with regard to specific embodiments. The benefits,advantages, solutions to problems, and any element or elements that maycause any benefit, advantage, or solution to occur or become morepronounced, however, are not to be construed as critical, required, oressential features or elements of any or all of the claims.

Moreover, embodiments and limitations disclosed herein are not dedicatedto the public under the doctrine of dedication if the embodiments and/orlimitations: (1) are not expressly claimed in the claims; and (2) are orare potentially equivalents of express elements and/or limitations inthe claims under the doctrine of equivalents.

1. A method of assembling a system in package comprising: placing aplurality of device components having different form factors on acarrier substrate; forming a molding compound layer over the devicecomponents, wherein a bottom surface of the device components iscoplanar with a bottom surface of the molding compound layer and theplurality of device components are embedded within the molding compoundlayer; curing the molding compound layer; removing the carriersubstrate; forming a single redistribution layer on the coplanar bottomsurfaces of the molding compound layer and the plurality of devicecomponents; forming a buildup layer on the single redistribution layer;forming a plurality of openings in the buildup layer; electricallybonding an active device die to the single redistribution layer of thepackage and directly vertically adjacent the plurality of devicecomponents; and singulating the system in package.
 2. The method ofclaim 1, further comprising placing a plurality of conductive bumpsalong a periphery of the single redistribution layer prior tosingulating the system in package.
 3. The method of claim 1, furthercomprising providing an underfill material between the active device dieand the buildup layer.
 4. The method of claim 1, further comprisingelectrically connecting the system in package to a circuit board withthe active device die between the single redistribution layer and thecircuit board.
 5. The method of claim 1, further comprising electricallyconnecting the system in package to a circuit board with the activedevice die over both the single redistribution layer and the circuitboard.
 6. The method of claim 1 wherein the active device die has aperiphery and wherein the plurality of device components is locatedwithin the periphery of the active device die.
 7. The method of claim 2wherein the plurality of conductive bumps comprise an inner core withinan outer shell.
 8. The method of claim 7 wherein the inner corecomprises copper and the outer shell comprises solder.
 9. The method ofclaim 1 wherein the active device die is electrically bonded to thesingle redistribution layer by a plurality of conductive bumps.
 10. Themethod of claim 1 wherein the active device die is electrically bondedto the single redistribution layer by a plurality of wire bonds.
 11. Themethod of claim 10 wherein the active device die has a first surfacenear the bottom surface of the molded compound layer and a secondsurface opposite the first surface, and wherein the plurality of wirebonds are electrically bonded to the second surface of the active devicedie.
 12. The method of claim 11 further comprising forming anencapsulation layer over the second surface of the active device die andover the plurality of wire bonds.
 13. A method of assembling a system inpackage comprising: placing a plurality of device components having formfactors on carrier substrate; forming a molding compound layer over thedevice components, wherein a bottom surface of the device components iscoplanar with a bottom surface of a molding compound layer and theplurality of the device components are embedded within the moldingcompound layer; removing the carrier substrate; forming a firstredistribution layer on a coplanar bottom surface of the moldingcompound layer and the plurality of device components; forming a builduplayer on the first redistribution layer; forming a plurality of openingsin the buildup layer; electrically bonding an active device die to thefirst redistribution layer of the package and directly verticallyadjacent to the plurality of device components; and forming a pluralityof conductive vias through the molding compound layer wherein theplurality of conductive vias contact the redistribution layer on thebottom surface of the molding compound layer and a second redistributionlayer on a top surface of the molding compound layer opposite the bottomsurface of the molding compound layer.
 14. The method of claim 13further comprising forming a second buildup layer on the secondredistribution layer; and forming a plurality of openings in the secondbuildup layer.
 15. The method of claim 13 further comprising forming aplurality of conductive bumps on the second redistribution layer. 16.The method of claim 15 further comprising electrically connecting theplurality of conductive bumps to a circuit board.
 17. The method ofclaim 13 further comprising curing the molding compound layer.
 18. Themethod of claim 13 further comprising singulating the system in package.19. The method of claim 13 wherein the active device die has a peripheryand wherein the plurality of device components is located within theperiphery of the active device die.
 20. A method of assembling a systemand package comprising: placing a plurality of device components havingdifferent form factors on a carrier substrate; forming a moldingcompound layer over the device component layer over the devicecomponents, wherein a bottom surface of the device components iscoplanar with a bottom surface of the molding compound layer and theplurality of device components are embedded within the molding compoundlayer; removing the carrier substrates; forming a redistribution layeron the coplanar bottom surface of the molding compound layer andplurality of device components; forming a buildup layer on theredistribution layer; forming a plurality of openings in the builduplayer; and electrically coupling an active device die to theredistribution layer of the package and directly vertically adjacent tothe plurality of device components.